--- Quote Start ---
Hi, is it possible to create data type with a custom width? Like in vhdl I can have std_logic_vector(17 downto 0). I didn't find anything in documentation. I know its not a standard in OpenCL, but it's quite important feature of fpga, maybe there is something specific. If not, are there any plans to do so?
--- Quote End ---
It's not explicitly possible in OpenCL like in VHDL, however the Altera Best Practices Guide does mention custom data type widths on page 16 in the discussion of Floating-Point versus Fixed-Point.
--- Quote Start ---
The OpenCL standard does not support fixed-point representation; you must implement fixed-pointrepresentations using integer data types. Hardware developers commonly achieve hardware savings byusing fixed-point data representations and only retain a data resolution required for performing calcula‐tions. You must use an 8, 16, 32, or 64-bit scalar data type because the OpenCL standard supports onlythese data resolutions. However, you can incorporate the appropriate masking operations in your sourcecode so that the hardware compilation tools can perform optimizations to conserve hardware resources.For example, if an algorithm uses a fixed-point representation of 17-bit data, you must use a 32-bit datatype to store the value. If you then direct the Altera Offline Compiler to add two 17-bit fixed-point valuestogether, the AOC must create extra hardware to handle the addition of the excess upper 15 bits. To avoidhaving this additional hardware, you can use static bit masks to direct the hardware compilation tools to disregard the unnecessary bits during hardware compilation.
--- Quote End ---
Essentially their example shows it all, but you need to use one of the OpenCL scalar data types and use static bitmasks to mask away the excess bits. It leaves all of the responsibility to the hardware compilation and I've never tested it, but it should work.
Honored Contributor
