Forum Discussion
ThomasTessier
Occasional Contributor
3 years agoCustom Built Avalon IP generating waitRequest but not being honored in the Interconnect.
I have a simple ArriaV based design using Quartus 21.1 that has a JTAG Master and BFM Master (for simulation). I am using a custom SPI module design that has a simple Avalon Slave interface. In my ...
ShengN_altera
Super Contributor
3 years agoHi,
One more thing is make sure there's proper wire connection between avm_waitrequest and slave_waitrequest like the .v file attached below. For example,
.avm_waitrequest (master_0_m0_waitrequest),
...
.avs_waitrequest (master_0_m0_waitrequest),
Similar problem is encountered if there's no proper wire connection.
Thanks,
Sheng