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ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Custom Built Avalon IP generating waitRequest but not being honored in the Interconnect.

I have a simple ArriaV based design using Quartus 21.1 that has a JTAG Master and BFM Master (for simulation). I am using a custom SPI module design that has a simple Avalon Slave interface. In my ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

Compared the posted simulation with the design example simulation (check image below), I noticed there're some differences between slave_write (posted simulation) and avs_write (design example simulation). The avm_waitrequest will be asserted and avm_writedata will only begin transferred during REQ_WRITE (write request) where avm_write will be '1'.

Thanks,

Best Regards,

Sheng