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ThomasTessier
Occasional Contributor
Occasional ContributorCustom Built Avalon IP generating waitRequest but not being honored in the Interconnect.
I have a simple ArriaV based design using Quartus 21.1 that has a JTAG Master and BFM Master (for simulation). I am using a custom SPI module design that has a simple Avalon Slave interface. In my ...
ThomasTessierOccasional Contributor
Occasional Contributor
The Blue Circle is showing wait_request occurring at the Avalon Master BFM when I read/write to an Altera GPIO block.
The Red Circle is showing my custom SPI controller generating wait_request but it never makes it to the Avalon Master BFM pins.
TomT...
