Critical Warning: Timing requirements for slow timing model timing analysis were not

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This warning indicates that your design (most likely) has a register to register path that exceeds the clock period. The message implies that your chip will possibly not function as intended if you program it. I say "possibly not function" since the timing model reports worst case operating conditions. The device may function at room temperature with an ideal power supply.

By consulting the timing report window, you will find out which path(s) are violating their requirements. This may result in one or more of the following actions:

* fixing false paths that are incorrectly constrained

* changing place & route optimization settings

* altering the design to meet timing requirements

* etc...

Timing closure is (sometimes) a very complicated problem. Without knowing more information about your particular design and/or failing paths, it is difficult to provide additional information.

- Mark

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thank you a lot.