Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- So how to deal with it? how to add timing constraints? how to decide how many timing constraints should I add? Thank you very much! --- Quote End --- I just had the same problem and had been trying to fix it for 2 days, finally done. If you are using Qsys or MegaFunction in your design, the Quartus seems to be very stupid, it will not automatically find the .sdc file by itself, to add them into your design, you have to select Assignment->TimeQuest Analyzer, then in the category find the TimeQuest Analyzer, add the .sdc files generated by Quratus for the IP cores, usually they are located in ../db/ip/submodules/.