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Altera_Forum's avatar
Altera_Forum
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11 years ago

Critical Warning (10237) can't infer register isn't issued for certain always blocks

Hello, I am having issues with the warning 10237. I understand its purpose and understand the incorrect code that can generate it. My issue is that I have seen instances where a synchronous code block has been replaced by combinatorial logic without a warning.

This code produces a warning: ""Critical Warning (10237): Verilog HDL warning at warnings.v(8): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead"" as it should: 

module warnings  
(input clk,   
input reset,   
input data_in,   
output reg q );  
  always @(posedge clk or negedge reset) q <= data_in;
endmodule

However this code does not produce a warning (and no registers are shown in the RTL viewer): 

module warnings 
(input clk, 
input rst, 
input  state, 
input  data, 
input  i, 
input  c, 
output reg  ia, 
output reg  ca );
always @(posedge clk or posedge rst) begin 
  case(state) 
  4'b0010, 4'b1100 : begin 
    ia <= i + data; 
    ca <= c + 8'b1; 
  end 
  default : begin 
    ia <= 'b0; 
    ca <= 'b0;            
  end 
 endcase 
end 
endmodule

Whereas this code does produce registers (as seen in gate-level simulations and in the RTL viewer): 

 
module warnings 
(input clk, 
input rst, 
input  state, 
input  data, 
input  i, 
input  c, 
output reg  ia, 
output reg  ca );
always @(posedge clk or posedge rst) begin 
  if (rst) begin 
     ia <= 'b0; 
     ca <= 'b0; 
  end 
  else begin 
  case(state) 
   4'b0010, 4'b1100 : begin 
      ia <= i + data; 
      ca <= c + 8'b1; 
    end 
   default : begin
     ia <= 'b0; 
     ca <= 'b0; 
   end 
  endcase 
end
end
endmodule

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Looks like a bug, as it looks like it should do the same as the first case. Please file a Service Request.

    (I tried the SystemVerilog always_ff hoping that might flag it, but no luck there either)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Quartus help shows following message

    CAUSE:

    In a Verilog Design File (.v) at the specified location, you used a Procedural Assignment in an Always Construct whose Event Control (sensitivity list) contains multiple edge triggers. Quartus II Integrated Synthesis attempted to infer a register for this assignment, but could not identify a unique clock signal from the list of edge triggers. Instead, Quartus II Integrated Synthesis generated combinational logic for this signal assignment. This error usually occurs when the control flow in the Always Construct does not distinguish the clock signal from the asynchronous control signals. For example, the Always Construct in the following code contains a single unconditional Procedural Assignment, but the Event Control contains two edge triggers:

    always @(posedge clk or negedge reset)

    begin

    q <= data_in;

    end

    Because the Always Construct does not contain any conditional logic to differentiate between clk and reset, the Quartus II software cannot identify the clock signal.

    Note : Naming has no impact when the Quartus II software identifies clock signals; the software identifies clock signals based only on the control flow in the Always Construct.

    ACTION:

    If you intended to infer a register for the Procedural Assignment, restructure the Always Construct to make the clock signal explicit. Refer to the Quartus II Help for information about correctly inferring synchronous logic using Verilog HDL. Otherwise, no action is required.