critical path and IC delay

Ideally if your problem is localised to part of design then you need to tackle it there. If however you reached the limit of your chip and the violation is random then the seed can help.

When the fitter starts it uses a default random seed value. You can change this seed and it will have up to 10% effect on timing. It is somewhere in the fitter settings.

You can also run several seeds overnight or weekend using the Design space explorer(DSE)

edit: Don't forget life is always random(Darwin knew that first, I wonder if nature used some tool like DSE and how long will it take it to end up as a butterfly cell nucleus)