critical path and IC delay

You are targetting Fmax of 200MHz and for your device you should get it readily unless your chip is really full. You can try the seed value if you don't want any redesign headaches.

Your thoughts about most critical path are not clear. The breakup into cell delay and interconnect delay doesn't help much in localising the problem. It may not be localised in the first place as floating timing violation may occur when chip reaches its limit.

I am not sure what you mean by (after routing...) I thought the timing analyser reports on issues after routing anyway.