critical path and IC delay

I have already optimized my design by adding registers to break the critical path between to registers , as a result of that, after placement step in quartus a message say me that :

Info: Estimated most critical path is memory to register delay of 5.293 ns

Info: Total cell delay = 2.658 ns ( 50.22 % )

Info: Total interconnect delay = 2.635 ns ( 49.78 % )

which is near of my goal of 5ns (200MHZ) , so for me it's good

BUT ! after the routing step the critical path is near of 6.3 ns and is made of 20% cell delay and 80% IC delay .... how can I avoid this ?

thanks