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Altera_Forum's avatar
Altera_Forum
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16 years ago

Creating partition issue

Hi guys: There is a mudule with bidrection pins (inout defined in VHDL) in my design, QII gave out error informations about this module when i created partition for this module. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Below is the error information:

Error: Net "dataint[15]", which fans out to "HostCom:inst3" is connecting a Partition with logic other than a single Bidirectional pin

Error: Net is fed by "inst3~6"

Error: Net is fed by "CtrlInt:inst1|DataInt[15]"

Error: Net is fed by "CtrlInt:inst1|DataInt[15]"