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Altera_Forum's avatar
Altera_Forum
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14 years ago

Creating Flip-flop by using logic gates

Hi, I am a student who new to VHDL and currently doing VHDL assignment. In this assignment, students are required to create the D, JK flip-flop. I need help to solve my error for my code ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Error (10500): VHDL syntax error at Dflip_flop.vhd(41) near text "end"; expecting ";", or an identifier ("end" is a reserved keyword)

Can anyone point out what is the syntax error here??

Thanks and appreciated for the helps.

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first of all, you need a semicolon on the end of the "end process" line.

Second of all, you'll have problems with this, as Q has multiple drivers. Q is driven from the process, and from W3. Are you sure you want the process there?

For the second question, what are you similating with? have you written a testbench?