Creating Flip-flop by using logic gates

Besides that, i also faced a prob when designing the JK flip-flop.

In this assignment, students are required to simulate the result in the functional and timing mode..

By using the code as shown as below:

-------------

library ieee;

use ieee.std_logic_1164.all;

library work;

entity JKflip_flop is

port

(

J :in std_logic;

K :in std_logic;

clk :in std_logic;

Q :out std_logic;

Qbar :out std_logic

);

end JKflip_flop;

architecture hc of JKflip_flop is

signal W1 : std_logic;

signal W2 : std_logic;

signal W3 : std_logic;

signal W4 : std_logic;

signal W5 : std_logic;

signal W6 : std_logic;

begin

Q <= W3;

Qbar <= W4;

W1 <= not (J and clk and W4);

W2 <= not (K and clk and W3);

W3 <= W1 nand W4;

W4 <= W2 nand W3;

end hc;

----------------

It can only simulate only in the timing mode and it show nothing in the functional mode. I cant find a reason y this will happened??

Anyone knows y tis happened?? Did it need any settings in quartus to make so that it can simulate in the functional mode???

Thank you.