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Altera_Forum's avatar
Altera_Forum
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17 years ago

Creating and encrypting netlists

I am trying to create a design for a customer that is part netlist, that they cannot edit, investigate or reverse engineer and part VHDL. They bought an algorithm that integrates into one of our boards that they wish to modify (it is an open source algorithm) but obviously we do not want them to get hold of our IP that contains memory interfaces, PCI core etc. I am trying to find out if it is possible to provide an encrypted netlist. I have found the steps to make a .qxp file, but dont understand if this is encrypted or not. Is it possible to view or edit a .qxp file?

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    A .qxp is not encrypted, but it is a binary format(i.e. it's not clear text for the design). Users can look at the contents in the technology map viewer and chip planner(the RTL viewer will show the same thing as the technology map viewer since the .qxp is post-synthesis, so high-level ideas like muxes will really just be a sea of LUTs and FFs). Bottom line is that it's do-able, but it would be really difficult.

    In the next release, coming out any day now, I believe there will be (.QXP as source), where you just give them the .qxp and it is read in directly. Right now you need to give them HDL(just a black-box wrapper).
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for the info.

    I have a further question about this. Is this file then family specific (eg. stratix 2, cyclone etc) or could it be used over a variety of families?

    If it is family specific, could a .qxp generated for a EP2S60 be used in a EP2S130, for example?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    It is family dependent, as the the underlying structure is post-synthesis, and potentially post-fit(depending on what you choose). That's one limitation for providing IP this way, in that it can be parameterized as the user can't resynthesize it.

    Within a family, it should work fine to re-fit for an EP2S130. (No guarantees when changing families, though it should be for straightforward reasons, i.e. if you go to a smaller part with fewer PLLs and you need more, it wouldn't fit.)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    A further question

    Would any of the namings from source code make their way into the netlist? That could give clues as the the purpose of various areas of logic?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Node names will be visible in timing analysis, Chip Planner, Technology Map Viewer, etc. Combinatorial node names are really difficult to figure out what they're doing since it's at the LUT level, but register names usually match your source code, so if you're worried about them sniffing stuff inside your logic, this is not a good solution at all. It's more of an impediment to them re-engineering your design. (And at that, it wouldn't pass any true security standards.) The .qxp wasn't really designed as a security feature, it just works nicely that way. I know Altera does have a way of protecting IP, but I'm sure there will be hoops to jump through...

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    There was a way to export a .vqm, but it's been disabled for newer families(or more specifically, it was never created.) Look under Assignments -> Settings -> Compilation. A .vqm is a Verilog file that is purely structural(i.e. it instantiates LUTs, FFs, etc.) I believe it is "flat" in that there is only one hierarchy, but all the node names imply hierarchy, i.e. you have a flop-flop whose name is top|hierA:instA|hierB:instB|count[2]. SYnplify and Precision are 3rd party synthesis tools that write out netlists too. (Synplify writes out .vqms too, while I think Precision writes out EDIFs. They have the same information, but I've found EDIFs much more difficult to understand)

    One thing you might want to google is "obfuscation". The idea is a tool that goes through your code and renames everything to nonsensical names, so what was original a state-machine with states idle, push_data, wait, and end_packet, would still be a state-machine but the names would be xhs, fafs, fafdsaf, fadasf, and hsdf. A synthesizer doesn't care about names, so you get the same results, but trying to decipher intent is much more difficult. You could provide obfuscated code(so the user would, in essence, have your source), or a .qxp after obfuscation. Just an idea.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Unfortunatly most of the source for this design is in BDF and AHDL, and theres alot of it, with quite a few levels of hierarchy. So any flattening and obfuscation would have to be done at the netlist stage.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    How concerned are you that the customer may try to reverse engineer your design? If it's a huge concern(say you have some killer IP that is your bread and butter), it may be worth putting a lot of work into this. If it's a case of "I doubt they'd ever do it, and if they did I'd be upset but progress fine", then maybe the .qxp or something like that is the best flow.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi all

    I'm reviving this thread since it is still relevant to me.

    I've supplied another company a qxp file, but I now I want to add a secret key to it.

    would it be possible for them to find out the value of this key?

    of course they can locate the FSM that uses it, but will they be able to locate this constant?

    I don't know if this is of any importance but I'm using quartus 8.1

    thanks in advance.