Creating and encrypting netlists

There was a way to export a .vqm, but it's been disabled for newer families(or more specifically, it was never created.) Look under Assignments -> Settings -> Compilation. A .vqm is a Verilog file that is purely structural(i.e. it instantiates LUTs, FFs, etc.) I believe it is "flat" in that there is only one hierarchy, but all the node names imply hierarchy, i.e. you have a flop-flop whose name is top|hierA:instA|hierB:instB|count[2]. SYnplify and Precision are 3rd party synthesis tools that write out netlists too. (Synplify writes out .vqms too, while I think Precision writes out EDIFs. They have the same information, but I've found EDIFs much more difficult to understand)

One thing you might want to google is "obfuscation". The idea is a tool that goes through your code and renames everything to nonsensical names, so what was original a state-machine with states idle, push_data, wait, and end_packet, would still be a state-machine but the names would be xhs, fafs, fafdsaf, fadasf, and hsdf. A synthesizer doesn't care about names, so you get the same results, but trying to decipher intent is much more difficult. You could provide obfuscated code(so the user would, in essence, have your source), or a .qxp after obfuscation. Just an idea.