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I dont quite follow this. According to the SOPC docs I need a master if I use the SDRAM IP. If this is the only slave why do I need a bridge? I thought that the bridge was to allow for multiple slaves? The docs imply that I can create my own master which is what I have done. The system compiles in SOPC without warning or errors. I have not tested it yet.
So are you saying that I need the bridge component between the external micro and my master device?
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The bridge is required when you want to connect an external (i.e. off-chip) peripheral. If you have an on-chip peripheral, then you don't need the tri-state bridge. In your specific case, if your SDRAM is an *external* chip which would communicate with the SOPC/NIOS system on the FPGA, then you certainly need a bridge. If the SDRAM is an on-chip component, say an IP core or an HDL design, then you don't have to use the bridge.
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