Forum Discussion
Occasional ContributorCreating a AXI master interface for New Platform component
What you've attached are just changes to the standard AXI behaviors, not specific signal roles. As you've found with the Component Editor, you must have certain signals and some at matching bus widths to follow the protocol for it to work as a custom component with an AXI interface.
Use the template to add all the signals in to your design and work from there. Platform Designer will only work with the true standard interface and the normal way that the signals are supposed to work, so "AXI-like" behavior wouldn't work unless you customize your component's logic to work with this (instead of relying on the interconnect to do it for you).
You say you're not familiar enough with AXI, but from looking at this, I think you may need get more information about the standard for yourself to make this work.
Occasional ContributorActually, I am trying to port NVDLA Architecture on FPGA. NVDLA has implemented an AXI like master interface to communicate with DRAM directly.
By "AXI like" I mean that few signals of AXI protocol are not implemented in and explanation for that is given in the nvdla_axi_assumptions.png file attached below. I don't have enough knowledge about AXI-protocol to understand the assumption given in the .png file.
@sstrell Could please go through the nvdla_axi_assumptions.png file and guide me on how to declare the logic for missing signals based on the information given in the file.
Super ContributorWhat you've attached are just changes to the standard AXI behaviors, not specific signal roles. As you've found with the Component Editor, you must have certain signals and some at matching bus widths to follow the protocol for it to work as a custom component with an AXI interface.
Use the template to add all the signals in to your design and work from there. Platform Designer will only work with the true standard interface and the normal way that the signals are supposed to work, so "AXI-like" behavior wouldn't work unless you customize your component's logic to work with this (instead of relying on the interconnect to do it for you).
You say you're not familiar enough with AXI, but from looking at this, I think you may need get more information about the standard for yourself to make this work.
