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You first post doesnt really tell us anything other than " it has a some logic with ram buffering between logic stages". This covers just above every FPGA project I have ever seen.
What are you actually trying to do? You can take your code and just instantiate it multiple times in your top level file...
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The actual purpose of my project is to perform edge detection on an input image. thats what the filters are for. the final output gets stored back in memory.
Yes, i understand the general concept that i can instantiate multiple instances of my entity. however, the concern i had was with how Altera IP such as the memory would handle that. I am currently initializing my 1 port ROM with my input image in it using a .HEX file. if i instantiate multiple copies will each copy of the rom start with the .hex file? if so i should be ok. if not, i might have to find a way to move the memory to my top level entity which means i will have to make major changes to my design which i am hoping to avoid doing.
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