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Altera_Forum's avatar
Altera_Forum
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10 years ago

Create multiple 'Cores' of my design

Hi, I have a design which does some image processing. I load an input image to a large Block RAM, process it using multiple filters and output it to another block RAM. I also use smaller block rams t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You first post doesnt really tell us anything other than " it has a some logic with ram buffering between logic stages". This covers just above every FPGA project I have ever seen.

What are you actually trying to do? You can take your code and just instantiate it multiple times in your top level file...