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a 1 port ram to store the output image doesnt make sense - it means it a write only ram, which would then imply the design has no output.
I was going to just write the output to it and then use the in system memory editor to read the image out. I already have the SW version written and working so i just need to compare the output of the VHDL to check.
You can copy any design as many times as you like in as many ways as you want, as long as you have enough resources. We have no ideas about the design, interfaces, code or any other design specs so you'll have to start asking some better questions and post some of your code and specs.
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The code is quite long thats why i didnt post it the first time. I did provide the high level details about my design in my original post. are there any other details needed to answer my question? if so i can provide those.
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