create_generated_clock

hello,

im driving a 1Hz clock out of the 50 MHz clock using divide by 25000000 counter, then I feed my design with the one hertz clock, the problem is when i try to constraint the 1Hz clock with create_generated_clock i got warnning saying that i have unconstraind Base clock which is my generated clock.

how come the timequest treate a generated clock as a base clock?

here is my counter

architecture behavioral of mytimer24 is

signal gnclk :std_logic:='0';

signal gncnt0,gncnt1 :integer range 0 to 59 :=0;

signal gncnt2 :integer range 0 to 23 :=0;

signal en0,en1 : std_logic;

begin

myclk : process(clk)

variable count : integer :=0;

begin

if clk'event and clk='1' then

count:=count + 1;

if count = 25000000 then

count :=0;

gnclk <= not gnclk;

end if;

end if;

end process;

and here is my constraints :

create_clock -name clk -period 20.000 [get_ports {clk}]

derive_pll_clocks

derive_clock_uncertainty

create_generated_clock -name gnclk -source [get_pins {gnclk|clk}] -divide_by 50000000 [get_pins {gnclk|q}]

and this is the warnning that i got when updating netlist :

Warning: Node: gnclk was determined to be a clock but was found without an associated clock assignment.

in the RTL i see that the gnclk (generated clock) is driven by regester gnclk clocked by the 50 MHz clock and an enable signal from a 25000000 counter

im new to the FPGA and timequest, I have read Rysc Timequest userguid although its really usefull and helped me alot but it more generlized.

I hope somone can help and thank you in advance.