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Altera_Forum
Honored Contributor
11 years agoThe structure of the vhdl file'm doing in quartus II and this thus:
library ieee; use ieee.std_logic_1164.all; entity is elevador15 port ( Clock, Reset: IN STD_LOGIC; C_orig: IN INTEGER RANGE 0 TO 15; C_dest: IN INTEGER RANGE 0 TO 15; E1_pos, E2_pos, E3_pos: OUT INTEGER RANGE 1 TO 15; E1_load, E2_load, E3_load: OUT INTEGER RANGE 0 TO 15 ); elevador15 end entity; ARCHITECTURE OF elevador15 single IS ** BEGIN PROCESS (reset, clock) BEGIN *** END PROCESS; END unique;