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Altera_Forum's avatar
Altera_Forum
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12 years ago

counting output pulse(project)

Hi everyone,

I would like to count the number of pulse outputting to a device, so that ,at some point, i can stop it from outputting. However i dont know how to do that..

I thought of using time to control the output signal, however it fails.

This question has been bothering me for 2-3 weeks, i still can't figure out. I hope you guys can help me. Thank you so much.

For more information,

I am actually building a system using FPGA to trigger the stepper motor in my lab. However, i want to stop the motor at some points, say 180 degree.

I have done all the calculation. In order to make it rotate 180 degree, i need to have 50 pulse outputting from FPGA.

Please help me. What should i do. Thank you

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    But why is it difficult to count 50 pulses. You need to explain the difficulty. are pulses equal in period?

  • Altera_Forum's avatar
    Altera_Forum
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    kaz,

    yes pulses are equal in period,

    like,, i need to stop it at some point, say 50 pulses...however i dont know how to do it , u have any idea?
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    kaz,

    yes pulses are equal in period,

    like,, i need to stop it at some point, say 50 pulses...however i dont know how to do it , u have any idea?

    --- Quote End ---

    50 pulses each n clocks (per pulse period) then you need to count 0 ~ 50n-1. reset counter at start and then enable counter when pulse is high only.

    I don't see what is so hard about it.
  • Altera_Forum's avatar
    Altera_Forum
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    oh sorry, but i am just a beginner, i tried

    should i use "repeat"?

    i can only use a counter to divide the frequency...

    and then i got stuck
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Sam,

    Please use this as reference.

    module pulse_atN(Clk, Reset, Pulse, N);

    parameter WIDTH = 10;

    input Clk, Reset;

    input [WIDTH-1:0] N;

    reg [WIDTH-1:0] Nlast;

    reg [WIDTH-1:0] Count;

    output Pulse;

    assign Pulse = (Count == N-1) && (N != 0);

    always @ (posedge Clk, posedge Reset)

    begin : PULSE_GENERATOR

    if(Reset)

    Count <= 0;

    else

    begin

    // nonblocking so check occurs with old Nlast

    Nlast <= N;

    if(Nlast != N)

    Count <= 0;

    else if(Count == N-1)

    begin

    Count <= 0;

    Pulse = 1;

    end

    else

    begin

    Count <= Count + 1;

    Pulse = 0;

    end

    end

    end

    endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    module pulse_atN(Clk, Reset, Pulse, N);

    parameter WIDTH = 10;

    input Clk, Reset;

    input [WIDTH-1:0] N;

    reg [WIDTH-1:0] Nlast;

    reg [WIDTH-1:0] Count;

    output Pulse;

    assign Pulse = (Count == N-1) && (N != 0);

    always @ (posedge Clk, posedge Reset)

    begin : PULSE_GENERATOR

    if(Reset)

    Count <= 0;

    else

    begin

    // nonblocking so check occurs with old Nlast

    Nlast <= N;

    if(Nlast != N)

    Count <= 0;

    else if(Count == N-1)

    begin

    Count <= 0;

    Pulse = 1;

    end

    else

    begin

    Count <= Count + 1;

    Pulse = 0;

    end

    end

    end

    endmodule