counting input signals

Well, it's pretty clear from the schematic that "inputs" is being used as the clock signal to lpm_counter0.

So, that part is pretty straightforward.

In your "bcd" and "leddisplay" have a weird sensitivity list: always @ (posedge data).

I'm not sure this behaviour can actually be mapped into hardware, since data is a bus, not a signal.

And in any case, it's not what you want. With this code, the output's will only change when one of the "data" bits goes from 0 to 1, but not the other way arround.

You problably want to use always @ (*) to describe combinational logic.

Finally, I advise against using latches in FPGAs as much as possible. Use a flip-flop with a clock enable.