counting input signals

Here goes nothin:

module tau(
input clk,
output reg Hz);
reg  cnt;
always @(posedge clk) begin
                        if (cnt == 50000000) begin
                                                cnt <= 0; 
                                                Hz <= 1;
                        end else begin
                                    cnt <= cnt+1;
                                    Hz <= 0;
                        end
end
endmodule 

module bcd(
input  data,
output reg  seg);
reg  z;
integer i;
always @(posedge data) begin 
            z = 0;
            z = data;
            
            for (i=0; i <= 6; i = i+1) begin
            
            if (z > 4) z = z + 3;
            if (z > 4) z = z + 3;
            if (z > 4) z = z + 3;
            z = z;
            end
            seg=z;
            end
            
endmodule 

module leddisplay(data, A1, B1, C1, D1, E1, F1, G1);
input  data;
output wire A1, B1, C1, D1, E1, F1, G1;
reg  first;
reg  Sevenseg1;
always @(posedge data) begin
        first <= data;
        
case(first)
    4'b0001: Sevenseg1 = 7'b0000110;  //1
    4'b0010: Sevenseg1 = 7'b1101101;  //2
    4'b0011: Sevenseg1 = 7'b1111001;  //3
    4'b0100: Sevenseg1 = 7'b0110011;  //4
    4'b0101: Sevenseg1 = 7'b1011011;  //5
    4'b0110: Sevenseg1 = 7'b0011111;  //6
    4'b0111: Sevenseg1 = 7'b1110000;  //7
    4'b1000: Sevenseg1 = 7'b1111111;  //8
    4'b1001: Sevenseg1 = 7'b1110011;  //9
    default: Sevenseg1 = 7'b0000000;
endcase
end 
assign {A1,B1,C1,D1,E1,F1,G1} = Sevenseg1;
endmodule

Leddisplay obviously only shows one digit, but ignore that.

Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected ripple clock "lpm_latch0:inst2|lpm_latch:lpm_latch_component|latches[0]" as buffer

Info: Detected ripple clock "bcd:inst3|seg[0]" as buffer

Info: Detected ripple clock "tau:inst1|Hz" as buffer