counter for 4096 quadrature ticks / revolution

Hi..I want to make counter for 4096 quadrature ticks / revolution.that means it will count 4096 ticks for one rotation of my Encoder shaft.

I dont know why my code is not working..Please look it n give me correction..

Code is

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use work.mem.all;

Entity single is

port(clk:in bit;

msbinv:in std_logic;

DOUT:in std_logic;

OUT_PUT1:out std_logic_vector(12 downto 1);

SCL:inout std_logic;

NSL :inout std_logic);

End Entity single;

Architecture single_calc of single is

signal counter : std_logic_vector(12 downto 1);

begin

trans:process(clk)

variable cnt : integer range 0 to 160;

begin

// code for 24 mhz to 4 mhz clock divider

if(clk'event and clk='1') then

cnt:=cnt +1;

if (cnt>=0 and cnt<3) then

NSL <= '1';

--cnt:= cnt+1;

elsif (cnt>=3 and cnt<6) then

NSL <='0';

SCL <= '0';

-- cnt := cnt + 1;

elsif (cnt>=6 and cnt<9) then

SCL <='1';

-- cnt := cnt + 1;

elsif (cnt>=9 and cnt<12) then

SCL <= '0';

--cnt := cnt + 1;

elsif (cnt>=12 and cnt<15) then

SCL <='1';

-- cnt := cnt + 1;

elsif (cnt>=15 and cnt<18) then

SCL <='0';

-- cnt := cnt + 1;

elsif (cnt>=18 and cnt<21) then

SCL <='1';

-- cnt := cnt + 1;

elsif (cnt>=21 and cnt<24) then

SCL <='0';

-- cnt := cnt + 1;

elsif (cnt>=24 and cnt<27) then

SCL <='1';

-- cnt := cnt + 1;

elsif (cnt>=27 and cnt<30) then

SCL <='0';

--cnt := cnt + 1;

elsif (cnt>=30 and cnt<33) then

SCL <='1';

-- cnt := cnt + 1;

elsif (cnt>=33 and cnt<36) then

SCL <='0';

elsif (cnt>=36 and cnt<39) then

SCL <='1';

elsif (cnt>=39 and cnt<42) then

SCL <='0';

elsif (cnt>=42 and cnt<45) then

SCL <='1';

elsif (cnt>=45 and cnt<48) then

SCL <='0';

elsif (cnt>=48 and cnt<51) then

SCL <='1';

elsif (cnt>=51 and cnt<54) then

SCL <='0';

elsif(cnt>=54 and cnt<57) then

SCL <='1';

elsif (cnt>=57 and cnt<60) then

SCL <='0';

elsif (cnt>=60 and cnt<63) then

SCL <='1';

elsif (cnt>=63 and cnt<66) then

SCL <='0';

elsif (cnt>=66 and cnt<69) then

SCL <='1';

elsif (cnt>=69 and cnt<72) then

SCL <='0';

elsif (cnt>=72 and cnt<75) then

SCL <='1';

elsif (cnt>=75 and cnt<78) then

SCL <='0';

elsif (cnt>=78 and cnt<81) then

SCL <='1';

elsif (cnt>=81 and cnt<84) then

SCL <='0';

elsif (cnt>=84 and cnt<87) then

SCL <='1';

elsif (cnt>=87 and cnt<90) then

SCL <='0';

NSL <= '1';

cnt:= 0;

end if;

end if;

end process trans;

// SCL toggle 13 times and at that time NSL is '0' ;

pros1:process(SCL,NSL)

begin

if(SCL'event and SCL='1') then

if NSL = '0' then

if(msbinv = '1') then

counter <= counter + "000000000001"; end if;

if (msbinv = '0') then

counter <= counter - "000000000001"; end if;

end if;

end if;

out_put1 <= counter ;

end process pros1;

End Architecture single_calc;

I would be thankful to you..

Thank you.