counte various value

after modification it compile successfully but simulation result is not correct

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use ieee.std_logic_signed.all;

use ieee.numeric_std.ALL;

entity rom1 is

port(CLK:in std_logic;

totalcoeffs,totalzeros:out std_logic_vector(4 downto 0);

trailingones:out std_logic_vector(1 downto 0));

end rom1;

architecture rom of rom1 is

signal etotalcoeffs : std_logic_vector(4 downto 0) := b"00000";

signal etotalzeros : std_logic_vector(4 downto 0) := b"00000";

signal etrailingones : std_logic_vector(1 downto 0) := b"00";

signal ecgt1 : std_logic := '0';

signal vin:signed(11 downto 0);

type ar is array (0 to 15) of signed(11 downto 0);

constant memory :ar:=

("111111111111","111111111111","000100000011","000000000100",

"000000000101","000000000110","000000000111","000000001000",

"000000001001","000000001010","000000001011","000100001000",

"000100000001","000100000010","000100001000","000100001000"

);

begin

process(CLK)

begin

if CLK'event and CLK = '1' then

x2:for i in 1 to 16 loop

vin <= signed(memory(i-1));

if vin /= 0 then

etotalcoeffs <= etotalcoeffs + 1;

elsif vin = 1 or vin = x"FFF" then

etrailingones <= etrailingones +1;

else

etotalzeros <= etotalzeros + 1;

end if;

end loop x2;

totalzeros <= etotalzeros;

totalcoeffs <= etotalcoeffs;

if (etrailingones > 3) then

trailingones <= b"11";

else

trailingones <= etrailingones;

end if;

end if;

end process;

end rom;