count 4 clock cycles

It doesn't look good. You should make a synchoronous design.

To detect de rise of a signal you may write:

process..

..

if(clk'event and clk = '1') then

q_reg <= q_next;

end if...

q_next <= And_out;

rise <= And_out and not q_reg;

when rise is '1' it means that And_out was '0' and now has a '1' ( rising edge ).

the counter:

proces...

if(clk'event and clk='1' )then

c_reg <= c_next;

end if;

...

c_next <= c_reg + 1 when ( c_reg = "00" and rise = '1' ) else

c_reg when ( c_reg = "00" ) else

c_reg + 1 when ( c_reg < 3 ) else

"00";

or something like this.