Correct way to use Components?

I want to use a component in my VHDL code but I'm not sure if I'm doing it correctly.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY CSA4Bit IS
	PORT (X : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		  Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		  CI: IN STD_LOGIC;
		  S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		  C4: OUT STD_LOGIC);
END CSA4Bit;
ARCHITECTURE Structure OF CSA4BIT IS
SIGNAL S1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL S2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT CLA4Bit
PORT
(
	A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    cin: IN STD_LOGIC;
    sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    cout: OUT STD_LOGIC
);
BEGIN
--If CI = 0
--Add with CLA with Cin of 0
--If CI = 1
--Add with CLA with Cin of 1
--Make sum = to whatever one I used
--Make C4 (the carry out) = to the carry out of whichever one I used
END Structure;

I don't have code in between BEGIN and END just comments but its complaining that there's an error near text "BEGIN"; expecting "end".

Other pertinent questions, can you use more than one component in a VHDL file? How would I do this? And also, does quartus have transmission gates so I can make a mux? (i'm not allowed to use megafunctions)