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Altera_Forum's avatar
Altera_Forum
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18 years ago

Correct way to use Components?

I want to use a component in my VHDL code but I'm not sure if I'm doing it correctly. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;...
Altera_Forum's avatar
Altera_Forum
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18 years ago

I used to be religious about putting my entities in separate files from my architectures, then using the Emacs VHDL-mode to create me a Modelsim makefile. However, I've now moved to combined files (even with packages in them when they relate to the entity in question) and using Modelsim to create the makefile.

For iterative compilation when debugging and I can use the "-just " option to vcom to compile only the architecture in a combined file.

I use Synplify for synthesis, but have not had occasion to try incremental compilation with it. I'll take you word for it on Quartus though :-)

Cheers,

Martin