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Altera_Forum
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11 years ago

Copying input signal to output through I/O buffers on Cyclone III

Hello Altera Forum community, I am an FPGA beginner trying to design a Cyclone III so that it outputs replica signals of a common input signal (also planning to implement a counter and a strobe...
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Altera_Forum
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11 years ago

I have found in the testbench that the clock period of the input "clk_in" (1ns) was shorter than the delay between the input and output (~7ns).

Much slower "clk_in" has allowed "clk_out" to follow the transition.

Thanks for taking time.

kima