Convolutional Interleaver: strange behaviour, any advice?

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/*DEINTERLEAVER*/
wire  data_in_de;
wire de_valid_in;
assign data_in_de=data_out;
assign de_valid_in=valid_out;
assign de_valid_out=de_valid_in;
reg  counter_reg, counter_reg1;
reg  clk_en_de;
/*Deinterleaver branches*/
reg DFF1;
reg DFF2 ;
reg DFF3 ;
reg DFF4 ;
reg DFF5 ;
reg DFF6 ;
reg DFF7 ;
reg DFF8 ;
reg DFF9 ;
reg DFF10;
reg DFF11;
reg DFF12;
reg DFF13;
reg DFF14;
reg DFF15;
reg DFF16;
reg DFF17;
reg DFF18;
reg DFF19;
reg DFF20;
reg DFF21;
reg DFF22;
reg DFF23;
reg DFF24;
reg DFF25;
reg DFF26;
reg DFF27;
reg DFF28;
reg DFF29;
reg DFF30;
reg DFF31;
reg DFF32;
wire  branch_in_de ;
reg  branch_out_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
assign branch_in_de = data_in_de;
/*counter delay to compensate data delay*/
always@(posedge clk)
begin
    counter_reg1<=counter;
    counter_reg<=counter_reg1; //compensate for branch_out and data_out
end
/*instantiate mux and enable control*/
mux_8x32 switch_deint(.counter(counter_reg), .branch_out(branch_out_de), .data_out(deinterleaver_out));
enable_coder en_bus_deint(.counter(counter), .clk_en(clk_en_de));
always@(posedge clk)
    begin
        if(de_valid_in)
            begin
            branch_out_de<=DFF1;
            branch_out_de<=DFF2;
            branch_out_de<=DFF3;
            branch_out_de<=DFF4;
            branch_out_de<=DFF5;
            branch_out_de<=DFF6;
            branch_out_de<=DFF7;
            branch_out_de<=DFF8;
            branch_out_de<=DFF9;
            branch_out_de<=DFF10;
            branch_out_de<=DFF11;
            branch_out_de<=DFF12;
            branch_out_de<=DFF13;
            branch_out_de<=DFF14;
            branch_out_de<=DFF15;
            branch_out_de<=DFF16;
            branch_out_de<=DFF17;
            branch_out_de<=DFF18;
            branch_out_de<=DFF19;
            branch_out_de<=DFF20;
            branch_out_de<=DFF21;
            branch_out_de<=DFF22;
            branch_out_de<=DFF23;
            branch_out_de<=DFF24;
            branch_out_de<=DFF25;
            branch_out_de<=DFF26;
            branch_out_de<=DFF27;
            branch_out_de<=DFF28;
            branch_out_de<=DFF29;
            branch_out_de<=DFF30;
            branch_out_de<=DFF31;
            branch_out_de<=DFF32;
           end
           else for(i=1;i<33;i=i+1)branch_out_de<=branch_out_de; //oppure non disturbare
    end
/* shift registers*/
always@(posedge clk)
    begin
        if(de_valid_in)
            begin
             case(clk_en_de)
            32'd2147483648:begin DFF1<=branch_in_de;end
            32'd1073741824:begin DFF2<=branch_in_de;DFF2<=DFF2;end
            32'd536870912:begin DFF3<=branch_in_de;DFF3<=DFF3;DFF3<=DFF3;end
            32'd268435456:begin DFF4<=branch_in_de;for(i=1;i<4;i=i+1)DFF4<=DFF4;end //1<=0,2<=1,3<=2
            32'd134217728:begin DFF5<=branch_in_de;for(i=1;i<5;i=i+1)DFF5<=DFF5;end
            32'd67108864:begin DFF6<=branch_in_de;for(i=1;i<6;i=i+1)DFF6<=DFF6;end
            32'd33554432:begin DFF7<=branch_in_de;for(i=1;i<7;i=i+1)DFF7<=DFF7;end
            32'd16777216:begin DFF8<=branch_in_de;for(i=1;i<8;i=i+1)DFF8<=DFF8;end
            32'd8388608:begin DFF9<=branch_in_de;for(i=1;i<9;i=i+1)DFF9<=DFF9;end
            32'd4194304:begin DFF10<=branch_in_de;for(i=1;i<10;i=i+1)DFF10<=DFF10;end
            32'd2097152:begin DFF11<=branch_in_de;for(i=1;i<11;i=i+1)DFF11<=DFF11;end
            32'd1048576:begin DFF12<=branch_in_de;for(i=1;i<12;i=i+1)DFF12<=DFF12;end
            32'd524288:begin DFF13<=branch_in_de;for(i=1;i<13;i=i+1)DFF13<=DFF13;end
            32'd262144:begin DFF14<=branch_in_de;for(i=1;i<14;i=i+1)DFF14<=DFF14;end
            32'd131072:begin DFF15<=branch_in_de;for(i=1;i<15;i=i+1)DFF15<=DFF15;end
            32'd65536:begin DFF16<=branch_in_de;for(i=1;i<16;i=i+1)DFF16<=DFF16;end
            32'd32768:begin DFF17<=branch_in_de;for(i=1;i<17;i=i+1)DFF17<=DFF17;end
            32'd16384:begin DFF18<=branch_in_de;for(i=1;i<18;i=i+1)DFF18<=DFF18;end
            32'd8192:begin DFF19<=branch_in_de;for(i=1;i<19;i=i+1)DFF19<=DFF19;end
            32'd4096:begin DFF20<=branch_in_de;for(i=1;i<20;i=i+1)DFF20<=DFF20;end
            32'd2048:begin DFF21<=branch_in_de;for(i=1;i<21;i=i+1)DFF21<=DFF21;end
            32'd1024:begin DFF22<=branch_in_de;for(i=1;i<22;i=i+1)DFF22<=DFF22;end
            32'd512:begin DFF23<=branch_in_de;for(i=1;i<23;i=i+1)DFF23<=DFF23;end
            32'd256:begin DFF24<=branch_in_de;for(i=1;i<24;i=i+1)DFF24<=DFF24;end
            32'd128:begin DFF25<=branch_in_de;for(i=1;i<25;i=i+1)DFF25<=DFF25;end
            32'd64:begin DFF26<=branch_in_de;for(i=1;i<26;i=i+1)DFF26<=DFF26;end
            32'd32:begin DFF27<=branch_in_de;for(i=1;i<27;i=i+1)DFF27<=DFF27;end
            32'd16:begin DFF28<=branch_in_de;for(i=1;i<28;i=i+1)DFF28<=DFF28;end
            32'd8:begin DFF29<=branch_in_de;for(i=1;i<29;i=i+1)DFF29<=DFF29;end
            32'd4:begin DFF30<=branch_in_de;for(i=1;i<30;i=i+1)DFF30<=DFF30;end
            32'd2:begin DFF31<=branch_in_de;for(i=1;i<31;i=i+1)DFF31<=DFF31;end    
            32'd1:begin DFF32<=branch_in_de;for(i=1;i<32;i=i+1)DFF32<=DFF32;end
            default: DFF1<=branch_in_de;
            endcase
            end
    end
endmodule