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Altera_Forum
Honored Contributor
16 years agoThere is no similar constraint because, "in theory" TimeQuest doesn't create clocks without a constraint, so if you don't constrain it to be a clock, it's not created.
That being said, I think derive_pll_clocks, which I recommend using, constrains this clock. Note that it is a real clock, as it's created by the JTAG controller(so something like SignalTap or Nios debugger runs off of it). That being said, it's not related to any other clocks in the design. I'm assuming your failing path has this as the clock for the source or destination register, but a different clock feeds the other one, so the problem is an incorrect clock relationship(all clocks are related by default in TimeQuest). You can unrelate it by doing: set_clock_groups -asynchronous -group {altera_reserved_tck} (Note that if you already have set_clock_groups in your .sdc, which I would also recommend, then add this as a separate group.