converting a signed shift amount to unsigned

Hi JenC

If you can provide a code example we may be able to help you better. In general latches are frowned upon in FPGA/ASIC design today. Many times these in-inadvertently occur in combinational always blocks with case statements, when no default case exists:

IE:

always @(*) begin

case (state_r)

3'b000 : output_c = 1'b1;

3'b001 : output_c = 1'b0;

endcase

end

In this case output_c is a latch, since there is no "default" in the case statement, output_r must hold it's previous value for all non-defined state_r conditions.

This can be fixed by defining a default condition like:

always @(*) begin

case (state_r)

3'b000 : output_c = 1'b1;

3'b001 : output_c = 1'b0;

default : output_c = 1'b0;

endcase

end

Or by pre-defining a default condition in the blocking assignments as:

always @(*) begin

output_c = 1'b0;

case (state_r)

3'b000 : output_c = 1'b1;

3'b001 : output_c = 1'b0;

endcase

end

The warning is telling you you have this kind of thing happening in your design. So you should be looking at it and seeing if you REALLY intended it to be a latch.

Pete

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I got a lot of warnings about combinational loops as latches of the design (via pipelining).

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Some confusion seems to be involved. Pipelining uses a clock and infers synchronous registers, never latches. Show the code!