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Altera_Forum
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12 years ago

converting a signed shift amount to unsigned

I got a lot of warnings about combinational loops as latches of the design (via pipelining). If the loops were created on purpose (e.g. iteration), Is this kind warning normal? Is there a way to remo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I got a lot of warnings about combinational loops as latches of the design (via pipelining).

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Some confusion seems to be involved. Pipelining uses a clock and infers synchronous registers, never latches. Show the code!