Convert Verilog Input file to VHDL

Quartus does not convert Verilog to VHDL. I believe it's only for schematic files. (Their used to be some tools out there for this, but the free ones never worked that well, i.e. you usually had to modify it some yourself). If it's pretty simple HDL, they may be fine, although if you know VHDL well it will not be hard to read. If it's complicated Verilog that uses the more abstract parts of the language, the tools may not work that well anyway. It's not like there is a clear 1:1 translation between all constructs, so if it gets complicated you probably don't want a tool converting it anyway.