Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Convert AHDL to Verilog

I have a design in AHDL for a keyboard scanner and I'm trying to convert this to Verilog. The AHDL code is in the enclosed ZIP "kbd.zip". The Verilog code is shown hereunder. The line "assig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

AHDL does an implied or of multiple assignments to the same variable.

So line 47 in kbd.tdf translates to something like this (I don't do Verilog well) 


assign lresult = ((sensecount == 0) && sense) || ((sensecount == 1) && sense)  || ((sensecount == 2) && sense)  || ((sensecount == 3) && sense) 
              || ((sensecount == 4) && sense) || ((sensecount == 5) && sense)  || ((sensecount == 6) && sense)  || ((sensecount == 7) && sense);

But I guess that a simple indexing works as well: 


assign lresult = sense;