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Altera_Forum
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16 years ago

Controlling the setting of IO pad delays

I have a design which uses a PLL to create an internal copy of an external clock used to interface a processor to a Cyclone II. The aim is to optimise the transfers to and from the processor by ensur...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Just a note to say that mostly worked, switching on "Optimise Multi-corner Timing" has persuaded Quartus to change the output delay to 1 and the input delay to 3. I expected 4 but the calculations are complex so within 1 step is understandable. Thanks very much for that.

George