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Altera_Forum
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16 years ago

Controlling the setting of IO pad delays

I have a design which uses a PLL to create an internal copy of an external clock used to interface a processor to a Cyclone II. The aim is to optimise the transfers to and from the processor by ensur...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Marvellous, thanks again. Setting the multi-corner optimisation has significantly improved the slack, I'll need to dig into the results to check the delays but I'm stuck in a meeting at the moment ;-)

George