Controller with counter [CPU - help]

The R/W must be set to '1' automatically in the fetch state to load the opcode to the instruction register. The fpgas works in asynchronous fashion, so u will get the instruction opcode in the next clock edge after you set RW ( next state ). For example:

process...

begin

-- default value

est_next <= est_reg;

ir_next <= ir_reg;

addr_bus <= pc(3 downto 0); -- only 4 bits of program counter are valid

rw <= '1';

case fetch is

...

when fetch =>

est_next <= decode;

addr_bus <= pc_reg(3 downto 0);

ir_next <= data_bus;

rw <= '1';

when decode =>

if( ir_reg = .... -- here you go through different state according to the opcode.