Control how symbel (.bsf) file is created from verilog (.v) file in Quartus II

Hi,

In using "Create symbol Files for current file" on my

cycloneIII_3c120_dev_niosII_standard_sopc.v, somehow

the behavior that the symbol is created changes.

I want to switch back to the old (before) way. But I do not know

how.

before: The ports for each sopc component (module)

locate in one isolated area (in the symbol) separated by

dotted lines. The dotted line are created automatically.

Only one bsf file (for current .v file) is created as the result of

the process.

now: Many bsf files (for all .v files under current .v file) are created.

In the top bsf file, all (in or out) ports for all sopc components are

together without separation by dotted line.

Anyone can help me on how to control the behavior of the operation?

Thanks,

gl888