continuous averaging using VHDL

I am puzzled now. What is then your data(11 downto 0)? isn't it adc data being converted as parallel word from the 12 bits serial stream?

sclk needs clock enable, where is your pulse that indicates data(11 downto 0) is ready? you need to put that pulse as if condition after sclk.

you really need to revise your thoughts carefully and write code yourself as otherwise we will stay going in circles. Good luck.