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Well I don't have the design with me now. I can check it on Monday. But what I tried today is that I was running my continuous average block on CS signal in the data sheet and the frequency for CS is 78.125KHz instead of normal clock of 20MHz and the result I get out of it was like before i-e 10mA, 20mA, 40mA,......100mA and the value gets stable after that. Is the for loop in the code increments on the rising edge of the clock?
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cs signal is only for activating adc and has nothing to do with data rate. You should use one clk(sclk) in your design. You should convert the 12 bits serial adc data to 12 bits word(parallel) and produce one pulse (for one sclk period) when word is ready then use this pulse to clock-enable the design.
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