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you don't need to compute the adc sampling rate. That is job of your design. Your logic that captures the 12 bits from adc must automatically get
the adc rate and you apply that rate(in logic, not by your figures) on the filter. It should then be whatever it is, possibly 1.25MHz/16 and I don't see how you got the figure 20. Anyway it is up to your logic to work out the sampling rate and you don't need to even know the rate.
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Well I don't have the design with me now. I can check it on Monday. But what I tried today is that I was running my continuous average block on CS signal in the data sheet and the frequency for CS is 78.125KHz instead of normal clock of 20MHz and the result I get out of it was like before i-e 10mA, 20mA, 40mA,......100mA and the value gets stable after that. Is the for loop in the code increments on the rising edge of the clock?
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