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The filter sampling rate must be exactly that of adc 12 bits data rate i.e. 19.5 KHz (if I am remember it correctly).
The sampling rate of a module is the clock rate as modified by any applied clock enable.
The best action is to simulate the filter on its own using the matlab model I posted and to simplify it you may inject a constant or any simple stream into both your design and matlab model and compare. They must match bitwise.
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@kaz
Ok I will check in MATLAB as well on monday.
The data sheet link for the ADC that I am using is:
http://www.ti.com/lit/ds/symlink/adc122s021.pdf If you see the data sheet for ADC, I previously thought that SCLK is 312KHz and if you see the timing diagram for ADC in the data sheet, it has a burst of 16 SCLK cycles so I came up with sampling rate of 312.5KHz/16=19.5KHz. But actually i was wrong. I checked it and the SCLK is 1.25MHz which means that the data rate should be 1.25MHz/16=78.125KHz or may be I think if you see the timing diagram in the ADC data sheet, there is an extra 4 SCLK cycles before the next burst comes out which means that filter sampling rate should be 1.25MHz/20= 62.5KHz. It means my average filter block should run on clock=62.5KHz according to timing diagram in data sheet(page 6 in the data sheet). Am I right? May be then I will get the 100mA directly instead of slow increment.
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