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@kaz,
I have figured it out that my average block was not running at all because I was running it at 20MHz and the done signal coming from SPI block is running on 78KHz which means I get the next data_in after every 78KHz. I am now running my average block on CS (78kHz) coming from spi master instead of normal clock of 20MHz. Now I am getting the result like before i-e 10mA, 20mA, 40mA,......100mA and the value gets stable after that. I am not sure but I think I need to further divide down the CS to 39KHz to get the 100mA directly. Am I right?
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The filter sampling rate must be exactly that of adc 12 bits data rate i.e. 19.5 KHz (if I am remember it correctly).
The sampling rate of a module is the clock rate as modified by any applied clock enable.
The best action is to simulate the filter on its own using the matlab model I posted and to simplify it you may inject a constant or any simple stream into both your design and matlab model and compare. They must match bitwise.
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