continuous averaging using VHDL

@kaz

data_in  : in  std_logic_vector (31 downto 0);
type type1 is array (1 to 255) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum: signed(19 downto 0) := (others => '0');
process (clk, reset)
begin
    if (reset = '1') then 
    out_val=0;
    stage <= (others => data_in(11 downto 0));
    sum <= resize(255 * signed(data_in(11 downto 0)), sum'length);
    elsif(rising_edge(clk)) then
    case state is
when out_1 =>
    if done='1' then
    data_out <= addr0 & bits;
    
    stage(1) <= data_in(11 downto 0);
for i in 2 to 255 loop
    stage(i) <= stage(i-1);
end loop;
-- subtract last stage from input
 sub_result <= resize(signed(data_in),13) - signed(stage(255));
-- accumulate
sum <= sum + sub_result;
adc_a_out <= std_logic_vector(sum(19 downto 8));
    state <= out_2;
    endif;
    end process;