continuous averaging using VHDL

@kaz

Two questions. The approach that I was using before for 32 samples, I increased that to 100 samples. I did following changes in the code:

data_in  : in  std_logic_vector (99 downto 0);
type type1 is array (1 to 99) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum: signed(19 downto 0) := (others => '0');
process (clk, reset)
begin
    if (reset = '1') then 
    state<=idle;
    out_val=0;
    out_val_2 <= 0;
    elsif(rising_edge(clk)) then
    case state is
when idle =>
    if req='1' then 
    state= out_1;
    end if;
when out_1 =>
    if done='1' then
    data_out <= addr0 & bits;
    
    stage(1) <= data_in(11 downto 0);
for i in 2 to 99 loop
    stage(i) <= stage(i-1);
end loop;
-- subtract last stage from input
 sub_result <= resize(signed(data_in),13) - signed(stage(99));
-- accumulate
sum <= sum + sub_result;
adc_a_out <= std_logic_vector(sum(19 downto 8));
    avg_1 <= '1'; 
    state <= out_2;
    endif;
    end case;
    end if;
    end process;

Can you tell if the number of bits for sum and sub_result are correct for 100 samples?

2nd question is related to the block average. I changed the 1024 samples to 32 samples and then averaging 5 blocks.

signal counter : integer 0 to 31 := 0;
signal data_in_d : signed(11 downto 0) := (others => '0');
signal sum: signed(16 downto 0) := (others => '0);
signal avg : std_logic_vector (11 downto 0);
type type1 is array (1 to 3) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum_new: signed(16 downto 0) := (others => '0');
process (clk, reset)
begin
    if (reset = '1') then 
    out_val=0;
    elsif(rising_edge(clk)) then
    
case state is
when out_1 =>
    if done='1' then
    data_out <= addr0 & bits;
    counter <= counter + 1;
    data_in_d <= signed(data_in);
    if counter /= 0 then
      sum <= sum + data_in_d;
    else
      sum <= (others => '0');
      avg <= std_logic_vector(sum(16 downto 5));
      stage(1) <= avg(11 downto 0);
for i in 2 to 4 loop
    stage(i) <= stage(i-1);
end loop;
-- subtract last stage from input
 sub_result <= resize(signed(avg),13) - signed(stage(4));
-- accumulate
sum_new <= sum_new + sub_result;
adc_a_out <= std_logic_vector(sum_new(16 downto 5));
    end if;
    state <= out_2;
    endif;
    end process;

Is the number of bits for sum and sum assignment to avg is correct?