continuous averaging using VHDL

@kaz

I think its better if I go with block average approach then because I don't want my resolution to be bad. As you said in one of the previous posts

"If so I will use block averager that only needs accumulator for 1024 samples then divide sum by discarding 10 LSBs at the end of each 1024 samples block then clear the sum and restart second block. You will get some segmentation of result(sharp corners) but you can then if you wish average the block results."

I don't have Quartus or FPGA board with me now. I will check it on Monday. Just to make sure and clear, can you modify the code for one state below for block averager and average the block results.

data_in  : in  std_logic_vector (31 downto 0);
type type1 is array (1 to 31) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum: signed(16 downto 0) := (others => '0');
process (clk, reset)
begin
    if (reset = '1') then 
    out_val=0;
    elsif(rising_edge(clk)) then
    case state is
when out_1 =>
    if done='1' then
    data_out <= addr0 & bits;
    
    stage(1) <= data_in(11 downto 0);
for i in 2 to 31 loop
    stage(i) <= stage(i-1);
end loop;
-- subtract last stage from input
 sub_result <= resize(signed(data_in),13) - signed(stage(31));
-- accumulate
sum <= sum + sub_result;
adc_a_out <= std_logic_vector(sum(16 downto 5));
    state <= out_2;
    endif;
    end process;