continuous averaging using VHDL

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@kaz

You mean to do the following:

data_in  : in  std_logic_vector (31 downto 0);
signal sum: signed(23 downto 0) := (others => '0');
signal sum2: signed(23 downto 0) := (others => '0');
process (clk, reset)
begin
    if (reset = '1') then 
    state<=idle;
    out_val=0;
    out_val_2 <= 0;
    elsif(rising_edge(clk)) then
    case state is
when idle =>
    if req='1' then 
    state= out_1;
    end if;
when out_1 =>
    if done='1' then
    data_out <= addr0 & bits;
    sum = sum - sum(22 downto 10) + data_in(11 downto 10);  
    adc_a_out <= std_logic_vector(sum(22 downto 11));
    state <= out_2;
    endif;
when out_2 =>
   if done='1' then
   data_out <= addr1 & bits;
   sum2 = sum2 - sum2(22 downto 10) + data_in(11 downto 10);  
   adc_b_out <= std_logic_vector(sum2(22 downto 11));
   state <= done_st;
   endif;
when done_st =>
    ack <='1';
    state <= idle;
when others =>
    state <= idle;
    end case;
    end if;
    end process;

Please correct me if I am wrong.

Thanks.

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The sum & sum2 are themselves the average, you don't need remove the 11 LSBs from them. You can keep all 23 bits since average need not be same width as data though I don't expect the mean of a good random signed signal to be higher than data.

However I did some modelling of 1024 stages and it does lose resolution badly so I suggest using this method for no more than 128 stages instead of 1024.